DocumentCode
3007047
Title
High-linear four-quadrant multiplier based on MOS weak-inversion region translinear principle with adaptive bias technique
Author
Tanno, Koichi ; Sugahara, Yuki ; Tamura, Hiroki
Author_Institution
Dept. of Electr. & Electron. Eng., Univ. of Miyazaki, Miyazaki, Japan
fYear
2011
fDate
21-24 Nov. 2011
Firstpage
680
Lastpage
684
Abstract
In this paper, we propose the high-linear four-quadrant analog multiplier based on MOS weak-inversion region. Because the proposed multiplier is based on the translinear principle, it is insensitive to the absolute accuracy of the devices and temperature variation. Furthermore, the proposed multiplier has very high linearity by adopting the adaptive bias technique. Simulations of the multiplier demonstrate a nonlinearity of 0.88%, a THD of 1.3%, a -3dB bandwidth of 768kHz, and a power consumption of 1.12μW under the condition that VDD = 1.0V.
Keywords
CMOS analogue integrated circuits; analogue circuits; low-power electronics; MOS weak-inversion region translinear principle; adaptive bias technique; four-quadrant CMOS analog multiplier; frequency 768 kHz; high-linear four-quadrant multiplier; power 1.12 muW; power consumption; voltage 1 V; Adaptation models; Bandwidth; CMOS integrated circuits; Linearity; MOSFETs; Mirrors; Simulation;
fLanguage
English
Publisher
ieee
Conference_Titel
TENCON 2011 - 2011 IEEE Region 10 Conference
Conference_Location
Bali
ISSN
2159-3442
Print_ISBN
978-1-4577-0256-3
Type
conf
DOI
10.1109/TENCON.2011.6129194
Filename
6129194
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