A study of pipelined pseudo-exhaustive testing on VLSI circuits with feedback

Author

Liou, Huoy-Yu ; Lin, Ting-Ting Y. ; Cheng, Chung-Kuan

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA

fYear

1994

fDate

19-23 Sep 1994

Firstpage

421

Lastpage

425

Abstract

An extensive empirical study on feedback paths in pipelined pseudo-exhaustive testing (PPET) is conducted. Feedback paths have impact on testing time for achieving certain fault coverage. Aliasing probability of looped PPET stays in O(2^-N) when N-bit CBITs are used as signature analyzer for test length longer than 2^N clock cycles. The overall testing time is then dominated by O(2^N) clock cycles for PPET. Our study proves PPET is an efficient solution for testing complex circuits and systems

Keywords

VLSI; automatic testing; circuit feedback; fault diagnosis; integrated circuit testing; logic testing; sequential circuits; VLSI circuits; aliasing probability; complex circuits; fault coverage; feedback; overall testing time; pipelined pseudo-exhaustive testing; signature analyzer; test length; Circuit faults; Circuit testing; Circuits and systems; Clocks; Feedback circuits; Feedback loop; Polynomials; System testing; Test pattern generators; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-2020-4

Type

conf

DOI

10.1109/ASIC.1994.404529

Filename

404529