Thermal Modeling of Quilt Packaging Interconnects

This paper discusses thermal reliability simulations of Quilt Packaging (QP), a novel chip-to-chip interconnect technology. A simulation model of QP is developed. The issue of reliability arises due to the different coefficients of thermal expansion (CTE) of materials used in the QP system for the operating temperature of circuits. Thermal stress is produced due to the CTE differences, the magnitude of which depends on the materials and dimensions of the structure. Simulation results work as guideline to obtain reliability data for QP structures.