Development of ESD robustness enhancement of a novel 800V LDMOS multiple RESURF with linear P-top rings

In this work, a novel 800V multiple RESURF LDMOS structures with or without P+ insertion region next to drain were developed to study the enhancement of ESD robustness. Compare to conventional RESURF LDMOS structures, the proposed multiple RESURF LDMOS without P+ insertion is able to achieve a specific on-resistance of lower than 130 mΩcm² while maintaining a breakdown voltage of over 800 volts. Furthermore, by using an additional P+ insertion next to drain, multiple RESURF LDMOS not only can improve the ESD robustness, which is demonstrated by the conventional 4 kV HBM testing but also increase the breakdown voltage higher than 900 volts. The thermal distribution of proposed structure was also studied under the ESD robustness testing using the thermodynamic mode simulation.