VLSI based design of a battery-operated digital hearing aid

Author

Morley, Robert E., Jr. ; Engel, George L. ; Sullivan, Thomas J. ; Natarajan, Sundaram M.

Author_Institution

Dept. of Electr. Eng., Washington Univ., St. Louis, MO, USA

fYear

1988

fDate

11-14 Apr 1988

Firstpage

2512

Abstract

A two-chip design is proposed wherein one chip is responsible for data acquisition and reconstruction while a second chip is dedicated to the digital signal-processing circuitry. A custom digital signal processor, potentially capable of performing over 3×10⁶ multiply accumulate operations per second while consuming less than a fraction of a milliwatt, that is required to implement a four-channel hearing aid, is presented. Power consumption is minimized while maintaining a wide dynamic range through the use of sign/logarithm arithmetic

Keywords

VLSI; acoustic signal processing; hearing aids; VLSI; battery-operated digital hearing aid; custom digital signal processor; data acquisition; data reconstruction; digital signal-processing circuitry; dynamic range; four-channel hearing aid; power consumption; sign/logarithm arithmetic; Auditory system; Circuits; Digital signal processing; Digital signal processing chips; Digital signal processors; Ear; Energy consumption; Microphones; Signal design; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1988. ICASSP-88., 1988 International Conference on

Conference_Location

New York, NY

ISSN

1520-6149

Type

conf

DOI

10.1109/ICASSP.1988.197154

Filename

197154