Behavioral fault simulation and ATPG, system for VHDL

Due to the increasing level of integration achieved by Very Large Scale Integrated (VLSI) technology, traditional gate-level fault simulation becomes more complex, difficult, and costly. Behavioral fault simulation at top functional level, described in a hardware description language, offers very attractive alternatives to these problems. This paper presents a new way to simulate the behavioral fault models for the Very high speed integrated circuits Hardware Description Language (VHDL). The performance analysis shows that relatively small number of test patterns generated by the behavioral fault simulation and Automatic Test Pattern Generation (ATPG) system detects around 98 percent of all testable gate-level faults