Design aspects of 10 to 40 Gb/s digital and analog Si-bipolar ICs

In this paper design aspects are discussed which allow one to exhaust the high speed potential of advanced Si bipolar technologies. Starting from the most promising circuit concepts and an adequate resistance level, the transistor geometries must be optimized very carefully using advanced transistor models. It is shown how the bond inductances can be favorably used and how the (critical) on-chip wiring must be taken into account. An inexpensive mounting technique proved to be well suited up to 50 Gb/s. The suitability of the design aspects discussed is confirmed by measurements of ICs for 10 and 40 Gb/s optical-fiber links.