Design of high performance CMOS charge pump for phase-locked loops synthesizer

Conventional charge pumps (CPs) all share a problem of current mismatching, which dominates the phase noise of phase-locked loop (PLL). A high performance charge pump circuit in 0.18¿m CMOS process is presented. A rail-to-rail error operational amplifier with reference circuit and self-biasing cascode current mirror enables the charge pump current to be well matched in a wide output voltage range. Simulation results show that the current mismatching can be less than 0.01% within output voltage range of 0.01V to 1.6V, with the charge pump current of 100¿A. The circuit dissipates 3mW from a single 1.8-V supply.