DocumentCode
3008336
Title
Timing skew insensitive switching for double sampled circuits
Author
Waltari, Mikko ; Halonen, Kari
Author_Institution
Electron. Circuit Design Lab., Helsinki Univ. of Technol., Espoo, Finland
Volume
2
fYear
1999
fDate
36342
Firstpage
61
Abstract
A novel switching arrangement is proposed to avoid the timing skew problems in double-sampled circuits. The modification is applied in a high-speed double-sampled S/H-circuit. Comparisons to a circuit with conventional switching show no degradation in circuit performance due to the modification. The validity of theoretical results is verified via fabrication and measurements of a prototype chip
Keywords
high-speed integrated circuits; sample and hold circuits; switched capacitor networks; circuit performance; double sampled circuits; high-speed S/H-circuit; switched-capacitor circuits; timing skew insensitive switching; Capacitors; Circuit optimization; Clocks; Electronic circuits; Energy consumption; Frequency; Sampling methods; Switches; Switching circuits; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location
Orlando, FL
Print_ISBN
0-7803-5471-0
Type
conf
DOI
10.1109/ISCAS.1999.780619
Filename
780619
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