DocumentCode
3008363
Title
VLSI Architecture for a real-time LPC-based feature extractor
Author
Barral, H. ; Moreau, N.
Author_Institution
ENST, Paris Cedex, France
Volume
11
fYear
1986
fDate
31503
Firstpage
381
Lastpage
384
Abstract
This paper describes a custom integrated circuit designed to perform LPC-based feature measurements. The chip is decomposed in 4 operators, working concurrently, implementing the functions of preem-phasizing, correlation, Parcor extraction and filtering. By using bit-serial architecture, each block can be adapted to the computation requirement. The projected chip complexity is approximately 25000 transistors (9 mm2 without I/O pads in 2µ NMOS technology) plus 2640 bits of RAM. The maximum sampling frequency is about 25 kHz which is sufficient for speech coding.
Keywords
Application specific integrated circuits; Computer architecture; Feature extraction; Filtering; Integrated circuit measurements; MOS devices; Performance evaluation; Sampling methods; Semiconductor device measurement; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '86.
Type
conf
DOI
10.1109/ICASSP.1986.1169185
Filename
1169185
Link To Document