Design of 0.13µm CMOS multi-valued analog to digital converter

A multi-valued logic outputs for analog to digital (ADC) have been implemented in this paper. The use of multiple-valued logic outputs for ADC design offers the possibility of an overall reduction in circuit complexity and size. The ADC generates multi-valued logic outputs rather than the conventional binary output system. The design implements current mode ADC architecture and is simulated using the model parameters for a standard 0.13μm CMOS process. The performance analysis of the design shows desirable performance parameters in terms of response, low power consumption, and a sampling rate of 500kHz at a supply voltage of 1.3V was achieved. The ADC design is suitable for digital wireless communication applications such as ultra wideband (UWB) and the needs of mixed-signal integrated circuit design and can be implemented as a conversion circuit for systems based on multiple-valued logic design.