A double-level-V/sub th/ select gate array architecture for multi-level NAND flash memories

This paper first explains that gate array noise during a bit-by-bit program verify operation, named source line noise, is estimated to have a crucial adverse effect on the threshold voltage (V/sub th/) control and causes a serious problem in Multi-Level NAND Flash Memories. Then a new array architecture, a Double-Level-V/sub th/ Select Gate Array Architecture, is introduced to eliminate this noise without cell area penalty.