• DocumentCode
    3009154
  • Title

    Verification methodology of compatible microprocessors

  • Author

    Yim, Joon-Seo ; Park, Chang-Jae ; Yang, Woo-Seung ; Oh, Hun-Seung ; Lee, Hee-Choul ; Choi, Hoon ; Kim, Tae-Hoon ; Lee, Seung-Jong ; Won, Nara ; Lee, Yung-Hei ; Park, In-Cheol ; Kyung, Chong-Min

  • Author_Institution
    Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
  • fYear
    1997
  • fDate
    28-31 Jan 1997
  • Firstpage
    173
  • Lastpage
    180
  • Abstract
    As the complexity of high-performance microprocessor increases, functional verification becomes more difficult and emerges as the bottleneck of the design cycle. In this paper, we suggest a functional verification methodology, especially for the compatible microprocessor design. To guarantee the perfect compatibility with previous microprocessors, we developed three C models in different representation levels, i.e., Polaris, MCV(Micro-Code Verifier) and StreC. C models are co-simulated with consistency checking between two different models. The simulation speed of C models makes it possible to test the “real-world” application programs on the RTL design with a software board model. To increase the confidence level of verifications, Profiler reports the verification coverage of the test vector, which is fed back to the automatic test program generator. Restartability feature also helps significantly reduce the total simulation time. Using the proposed verification methodology, we designed and verified an Intel 486-compatible microprocessor successfully
  • Keywords
    automatic programming; computational complexity; formal verification; microprocessor chips; C models; MCV; Polaris; RTL design; StreC; automatic test program generator; compatible microprocessors; confidence level; consistency checking; design cycle; functional verification; high-performance microprocessor; perfect compatibility; simulation speed; software board model; verification methodology; Application software; Automatic programming; Automatic testing; Clocks; Computer bugs; Design methodology; Discrete event simulation; Formal verification; Hardware design languages; Microprocessors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific
  • Conference_Location
    Chiba
  • Print_ISBN
    0-7803-3662-3
  • Type

    conf

  • DOI
    10.1109/ASPDAC.1997.600108
  • Filename
    600108