Fast barrier synchronization hardware

Author

Beckmann, Carl J. ; Polychronopoulos, Constantine D.

Author_Institution

Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA

fYear

1990

fDate

12-16 Nov 1990

Firstpage

180

Lastpage

189

Abstract

A special-purpose hardware scheme uniquely tailored to barrier synchronization is presented. It allows barrier synchronization to be performed within a single instruction cycle for moderately sized systems, and is scalable with logarithmic increase in synchronization time. It supports a large number of concurrent barriers, and can also be used to support a number of different barrier synchronization schemes. The hardware is relatively simple and inexpensive. Simulation results have shown that, under reasonable assumptions, it can decrease typical parallel-loop execution time significantly, especially for fine-grained and statically scheduled loops

Keywords

concurrency control; microcomputers; parallel programming; synchronisation; barrier synchronization; concurrent barriers; parallel-loop execution time; register-based barrier synchronisation; statically scheduled loops; synchronization time; Costs; Counting circuits; Delay; Hardware; Large-scale systems; Multiprocessor interconnection networks; Parallel machines; Processor scheduling; Research and development; US Department of Energy;

fLanguage

English

Publisher

ieee

Conference_Titel

Supercomputing '90., Proceedings of

Conference_Location

New York, NY

Print_ISBN

0-8186-2056-0

Type

conf

DOI

10.1109/SUPERC.1990.130019

Filename

130019