A GaAs MESFET 7 Gb/s dynamic decision circuit IC

Author

Bayruns, R.J. ; Chen, A.D.M. ; Gilbert, J. ; Goyal, R. ; Wang, Jiacheng

Author_Institution

Anadigics Inc., Warren, NJ, USA

fYear

1988

fDate

24-25 May 1988

Firstpage

27

Lastpage

30

Abstract

A GaAs MESFET dynamic decision circuit is reported that was operated at up to 7 Gb/s. A block diagram of the flip-flop is shown along with a detailed schematic diagram. The circuit consists basically of two differential amplifiers and two sample-and-hold gates operating in a manner similar to a master-slave D flip-flop. The circuit uses 0.5- mu m-gate GaAs MESFET technology and charge-cancelling techniques to obtain the 7-Gb/s clocking rate. A 0.6-V peak-to-peak output data eye is symmetrical and has 70 ps rise and fall times while retiming a noisy data input. The circuit operates from a single -6 V supply and dissipates 0.24 W of power. The chip´s size is 0.5 mm/sup 2/.<>

Keywords

III-V semiconductors; field effect integrated circuits; flip-flops; gallium arsenide; integrated logic circuits; optical communication equipment; 0.24 W; 0.5 micron; 7 Gbit/s; 70 ps; GaAs; MESFET dynamic decision circuit; charge-cancelling techniques; clocking rate; differential amplifiers; fall times; flip-flop; peak-to-peak output data eye; power dissipation; rise time; sample-and-hold gates; Capacitors; Clocks; Differential amplifiers; Flip-flops; Gallium arsenide; MESFET circuits; MESFET integrated circuits; Resistors; Variable structure systems; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave and Millimeter-Wave Monolithic Circuits Symposium, 1988. Digest of Papers., IEEE 1988

Conference_Location

New York, NY, USA

Type

conf

DOI

10.1109/MCS.1988.197282

Filename

197282