Title :
50,000 gate ASIC prototyping PLD using four flex 8000 devices and a programmable interconnect
Author :
Terrill, Richard
Author_Institution :
Altera Corp., San Jose, CA, USA
Abstract :
Gate array designs are usually simulated to catch logic errors prior to silicon production. Emulation, or implementation and testing of the custom design in reprogrammable hardware, provides more exhaustive evaluation of design accuracy, but most hardware emulation systems are large and expensive. This paper presents a 50,000-gate programmable logic device (PLD) that has been developed to support medium density gate array emulation inexpensively, and in a small form-factor
Keywords :
application specific integrated circuits; circuit CAD; integrated circuit design; integrated circuit interconnections; integrated circuit testing; logic CAD; logic partitioning; logic testing; programmable logic arrays; ASIC prototyping PLD; custom design; flex 8000 devices; gate array design; medium density gate array emulation; programmable interconnect; programmable logic device; Application specific integrated circuits; Emulation; Hardware; Logic arrays; Logic design; Logic devices; Production; Programmable logic arrays; Prototypes; Silicon;
Conference_Titel :
ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-2020-4
DOI :
10.1109/ASIC.1994.404543
