Title :
A submicron triple-level-metal gate array process utilizing tungsten for 1st level interconnect
Author :
Manos, Pete ; Pintchovski, Fabio ; Klein, Jeff ; Travis, Ed ; Boeck, Bruce ; Woo, Michael ; Chen, Chunshing ; Koenigseder, Sig ; Dillard, Rick
Author_Institution :
Motorola Inc., Austin, TX, USA
Abstract :
A novel triple-level-metal process, utilizing tungsten for first-level metallization, has been developed for use in submicron arrays. The contact barrier is a composite layer of sputtered and CVD TiN, providing for good adhesion of the blanket tungsten layer. Other process modules include tapered contact and via etches, dyed resist for fine-line patterning, reflowed BPSG for first ILD and via-1, and low-stress nitride passivation, providing for void-free metallization for all three layers. Prototype 1.0-μm gate arrays have been fabricated using this technology
Keywords :
VLSI; integrated circuit technology; metallisation; titanium compounds; tungsten; 1 micron; B2O3-P2O5-SiO2; CVD; W-TiN; adhesion; contact barrier; dyed resist; fine-line patterning; first-level metallization; low-stress nitride passivation; reflowed BPSG; sputtering; submicron triple-level-metal gate array process; void-free metallization; Adhesives; Application specific integrated circuits; Circuit testing; Contacts; Integrated circuit interconnections; Manufacturing processes; Metallization; Temperature; Tin; Tungsten;
Conference_Titel :
VLSI Multilevel Interconnection Conference, 1989. Proceedings., Sixth International IEEE
Conference_Location :
Santa Clara, CA
DOI :
10.1109/VMIC.1989.78074
