A triple metal interconnection process for CMOS technology

Author

Cagnoni, P. ; Gualandris, F. ; Masini, L.

Author_Institution

ST Microelectron., Agrate, Italy

fYear

1989

fDate

12-13 Jun 1989

Firstpage

47

Lastpage

54

Abstract

A triple interconnection process suitable for a CMOS 1.2-μm technology device is described. As far as process technology is concerned, planarization was applied at contacts and via I and II levels. In order to avoid silicon grains in the contact and to improve contact resistance, the metallization scheme requires the use of a metallization barrier. The AlSi(1%)Cu(0.5%) alloy was used for the metal I, II, and III interconnection layers. In order to accomplish gettering and deal with stress issues, APCVD PSG 4-m/o P₂O₅ and PECVD oxynitride (refractive index 1.75) were used for the final passivation. The triple metal interconnection impact on contact and transistor performances was evaluated by the use of Kelvin measurements and the 10% variation of the normalized transconductance, respectively

Keywords

CMOS integrated circuits; aluminium alloys; contact resistance; copper alloys; integrated circuit technology; metallisation; silicon alloys; 1.2 micron; APCVD; AlSiCu; CMOS technology; Kelvin measurements; P2O5-SiO2; PECVD oxynitride; PSG; contact resistance; gettering; interconnection layers; metallization barrier; passivation; planarization; process technology; stress; transconductance; triple metal interconnection process; via levels; CMOS process; CMOS technology; Contact resistance; Gettering; Metallization; Passivation; Planarization; Refractive index; Silicon; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Multilevel Interconnection Conference, 1989. Proceedings., Sixth International IEEE

Conference_Location

Santa Clara, CA

Type

conf

DOI

10.1109/VMIC.1989.78075

Filename

78075