High-speed interfaces for analog, iterative VLSI decoders

Author

Helfenstein, Markus ; Lustenberger, Felix ; Loelige, Andrea ; Tarköy, Felix ; Moschytz, George S.

Author_Institution

Inst. for Signal & Inf. Process., Eidgenossische Tech. Hochschule, Zurich, Switzerland

Volume

2

fYear

1999

fDate

36342

Firstpage

428

Abstract

The design of various high-speed interface architectures for off-chip connections to and from analog, iterative VLSI decoders is discussed. It is shown that for applications with high transmission rates and low to medium accuracy, MOSFET-only R-2R ladders in combination with switched-current memory cells are ideally suited, due to their current mode nature as well as their power and area efficiency. It is expected that data rates well above 100 MS/s can be obtained

Keywords

VLSI; analogue processing circuits; current-mode circuits; iterative decoding; switched current circuits; MOSFET-only R-2R ladders; area efficiency; current mode nature; data rates; high-speed interfaces; iterative VLSI decoders; off-chip connections; switched-current memory cells; transmission rates; Circuits; Computer networks; Energy consumption; Information processing; Iterative decoding; Signal design; Signal processing; Signal to noise ratio; Very large scale integration; Video signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.780754

Filename

780754