A 200-MHz CMOS bit-serial neural network

Author

Johansson, Henrik O. ; Larsson, Patrik ; Larsson-Edefors, Per ; Svensson, Christer

Author_Institution

LSI Design Center, Linkoping Univ., Sweden

fYear

1994

fDate

19-23 Sep 1994

Firstpage

312

Lastpage

315

Abstract

Implementing neural network hardware is a challenging task with tough requirements on computation and communication. We explore a time-multiplexed architecture with both bit-serial communication and computation, SINN (Serially Implemented Neural Network), for which the main goal is a high computation/area ratio. On-chip learning is excluded since this is a waste of hardware resources during run-time for many applications. Our experience is that an optimized bit-serial implementation has smaller area, while power consumption is increased, compared to a parallel structure

Keywords

CMOS digital integrated circuits; feedforward neural nets; learning (artificial intelligence); neural chips; recurrent neural nets; 200 MHz; CMOS bit-serial neural network; SINN; bit-serial communication; bit-serial computation; computation/area ratio; hardware resources; neural network hardware; on-chip learning; parallel structure; power consumption; serially implemented neural network; time-multiplexed architecture; Broadcasting; Computer networks; Decoding; Engines; Hardware; Joining processes; Neural networks; Neurons; Pipeline processing; Runtime;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-2020-4

Type

conf

DOI

10.1109/ASIC.1994.404551

Filename

404551