Efficient TWIN-VQ audio decoder implementation on a configurable processor using instruction extension

Transform-domain Weighted INterleave Vector Quantization(TwinVQ)is one of the coding tools adopted in MPEG-4 audio standard. In this paper, we present an efficient implementation of TwinVQ decoder on a configurable processor (Tensilica Xtensa). To achieve real time execution, two measures are adopted, i.e. fast computing algorithm and customized instruction extension. We first determine the setting of the base processor configuration and conduct a system profiling to identify the critical section of the program. Customized instructions are developed to speed up the execution of inverse modified discrete cosine transform (IMDCT). Techniques such as parallel processing, loop unrolling, multi-cycle execution and hardware sharing are employed in designing these instructions. Simulation results indicate an almost one half MIPS number reduction (from 321 to 171) with the help of instruction extension. The incurred hardware overhead is less than 10K logic gates -only about one half that of the base processor.