Title :
The reconfigurable arithmetic processor
Author :
Fiske, Stuart ; Dally, William J.
Author_Institution :
Lab. for Comput. Sci., MIT, Cambridge, MA, USA
fDate :
30 May-2 Jun 1988
Abstract :
The reconfigurable arithmetic processor (RAP), an arithmetic processing node for a message-passing, MIMD (multiple-input, multiple-data-stream) concurrent computer, is described. It incorporates on one chip several serial, 64-bit floating-point arithmetic units connected by a switching network. By sequencing the switch through different patterns, the RAP chip calculates complete arithmetic formulas. By chaining together its arithmetic units, the RAP reduces the amount of off-chip data transfer. Simulations have shown that off-chip I/O can often be reduced to 30% or 40% of that required by a conventional arithmetic chip. A peak performance of 20 MFLOPS (million floating-point operations per second) with 800-Mb/s off-chip bandwidth in 2-μm CMOS process is predicted
Keywords :
computer architecture; digital arithmetic; 2 micron; 2-μm CMOS process; 20 MFLOPS; MIMD concurrent computer; arithmetic processing node; floating-point arithmetic units; message-passing; off-chip data transfer; reconfigurable arithmetic processor; Analytical models; Bandwidth; CMOS process; Computational modeling; Concurrent computing; Digital arithmetic; Equations; Floating-point arithmetic; Laboratories; Registers; Switches;
Conference_Titel :
Computer Architecture, 1988. Conference Proceedings. 15th Annual International Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
0-8186-0861-7
DOI :
10.1109/ISCA.1988.5207
