A parallel algorithm for state assignment of finite state machines

Author

Hasteer, Gagan ; Banerjee, Prithviraj

Author_Institution

Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA

Volume

2

fYear

1996

fDate

12-16 Aug 1996

Firstpage

37

Abstract

Optimization of huge sequential circuits has become unmanageable in CAD of VLSI due to enormous time and memory requirements. In this paper, we report a parallel algorithm for the state assignment problem for finite state machines. Our algorithm has three significant contributions: It is an asynchronous parallel algorithm portable across different MIMD machines. Time and memory requirements reduce by a factor of P (the number of processors), enabling it to handle large problem sizes which the sequential algorithm fails to handle. The quality of the results for multiprocessor runs remains comparable to the sequential algorithm on which it is based

Keywords

VLSI; circuit CAD; finite state machines; optimisation; parallel algorithms; sequential circuits; state assignment; asynchronous parallel algorithm; finite state machines; memory requirements; parallel algorithm; sequential algorithm; sequential circuits optimisation; state assignment; time requirements; Automata; Circuit synthesis; Concurrent computing; Contracts; Design automation; Encoding; Parallel algorithms; Parallel processing; Sequential circuits; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel Processing, 1996. Vol.3. Software., Proceedings of the 1996 International Conference on

Conference_Location

Ithaca, NY

ISSN

0190-3918

Print_ISBN

0-8186-7623-X

Type

conf

DOI

10.1109/ICPP.1996.537379

Filename

537379