A high resolution digital CMOS time-to-digital converter based on nested delay locked loops

This paper describes an integrated digital CMOS time-to-digital converter, TDC, with sub-gate-delay LSB width and 50 ps single shot resolution which equals 7 mm in time-of-flight laser range-finding measurement. The circuit was fabricated in an 0.8 μm standard digital CMOS process. The measurement is based on a counter and a novel two step parallel interpolation that uses only 32 delay elements in two nested 16 element delay locked loops to provide 128 LSBs in the interpolator that resolves the timing within the reference clock cycle. The TDC has a fast conversion rate because of flash principle and requires no external calibration because the delay elements used for timing have been delay locked to the reference clock period. This TDC also has a very good temperature stability of 0.03 ps/°C and a low current consumption of <20 mA from a +5 V supply