Title :
Design of high-performance CMOS charge pumps in phase-locked loops
Author_Institution :
Conexant Syst. Inc., Newport Beach, CA, USA
Abstract :
Practical considerations in the design of CMOS charge pumps are discussed. The non-ideal effects of the charge pump due to the leakage current, the mismatch, and the delay offset in the P/FD are quantitatively analyzed. To use the appropriate charge pump in various PLL applications, several architectures are investigated and their performances are compared. The improved design of both the single-ended and the differential charge pumps are presented with the simulation result
Keywords :
CMOS analogue integrated circuits; integrated circuit design; leakage currents; phase locked loops; CMOS charge pump design; PLL applications; delay offset; differential charge pumps; high-performance charge pumps; leakage current; mismatch; nonideal effects; phase-locked loops; single-ended charge pumps; Bandwidth; Charge pumps; Clocks; Frequency synthesizers; Leakage current; Passive filters; Phase locked loops; Signal design; Timing; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.780807
