A combined channel and hardware noise resilient Viterbi decoder

Author

Hussien, Amr M A ; Khairy, Muhammed S. ; Khajeh, Amin ; Amiri, Kiarash ; Eltawil, Ahmed M. ; Kurdahi, Fadi J.

Author_Institution

Univ. of California Irvine, Irvine, CA, USA

fYear

2010

fDate

7-10 Nov. 2010

Firstpage

395

Lastpage

399

Abstract

Recent power reduction techniques aggressively modulate the supply voltage of embedded buffering memories allowing acceptable hardware errors to flow through the processing chain. In this paper, we present a model that captures the statistics of both channel noise and hardware failures. We further introduce a modified Viterbi decoder that maximizes the likelihood of the received data based on the distribution of the combined noise. Simulation results show a consistent improvement in BER performance across all SNRs with an area overhead ranging from 0.65% to 3.26% compared to the conventional Viterbi decoder when synthesized using a 65 nm standard library.

Keywords

Viterbi decoding; codecs; error statistics; area overhead; bit error rate; channel noise; embedded buffering memories; hardware failure; hardware noise resilient Viterbi decoder; Bit error rate; Decoding; Hardware; Measurement; Signal to noise ratio; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers (ASILOMAR), 2010 Conference Record of the Forty Fourth Asilomar Conference on

Conference_Location

Pacific Grove, CA

ISSN

1058-6393

Print_ISBN

978-1-4244-9722-5

Type

conf

DOI

10.1109/ACSSC.2010.5757543

Filename

5757543