Title :
A crossing charge recycle refresh scheme with a separated driver sense-amplifier for Gb DRAMs
Author :
Naritake, I. ; Sugibayashi, T. ; Utsugi, S. ; Murotani, T.
Author_Institution :
ULSI Device Dev. Labs., NEC Corp., Kanagawa, Japan
Abstract :
A crossing charge recycle refresh (CCRR) scheme is proposed for large capacity DRAMs with hierarchical bit-line architecture, which reduces main bit-line charging current to 25% of that of conventional DRAMs. A separated driver sense-amplifier (SDSA) circuit is essential to realize this scheme because it features 11 times shorter charge transfer period than that of conventional sense amplifiers. These circuits are applied to an experimental 1-Gb DRAM.
Keywords :
CMOS memory circuits; DRAM chips; 1 Gbit; Gb DRAMs; bit-line charging current reduction; charge transfer period; crossing charge recycle refresh scheme; hierarchical bit-line architecture; large capacity dynamic RAM; separated driver sense-amplifier; Charge transfer; Driver circuits; Low voltage; National electric code; Operational amplifiers; Power dissipation; Random access memory; Recycling; Timing; Ultra large scale integration;
Conference_Titel :
VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
0-7800-2599-0
DOI :
10.1109/VLSIC.1995.520705
