DocumentCode
3012582
Title
Digital background calibration of redundant split-flash ADC in 45nm CMOS
Author
Majidi, Rabeeh ; Crasso, Anthony ; McNeill, John A.
Author_Institution
Electrical and Computer Engineering Department, Worcester Polytechnic Institute, MA 01609, USA
fYear
2012
fDate
20-23 May 2012
Firstpage
1271
Lastpage
1274
Abstract
This paper presents a redundant flash ADC using a “Split-ADC” calibration structure and lookup-table-based correction. ADC input capacitance is minimized through use of small, power efficient comparators; redundancy is used to tolerate the resulting large offset voltages. Correction of errors and estimation of calibration parameters are performed in the background in the digital domain. This 5.8 ENOB flash ADC is designed for a sampling rate of 1Gs/s in 45nm SOI CMOS.
Keywords
Calibration; Convergence; MATLAB; Table lookup; Wireless communication;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location
Seoul, Korea (South)
ISSN
0271-4302
Print_ISBN
978-1-4673-0218-0
Type
conf
DOI
10.1109/ISCAS.2012.6271469
Filename
6271469
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