A low-power 10-bit 50-MS/s SAR ADC using a parasitic-compensated split-capacitor DAC

This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC). To reduce power and area, the monotonic switching procedure is combined with a parasitic-compensated split-capacitor DAC that also has an improved capacitor matching. The nonlinearity of the conventional split-capacitor DAC due to parasitic capacitance and capacitor mismatch is improved by modifying the capacitor bank so that the bridge capacitor is an integer multiple of the unit capacitor (as opposed to fractional multiple in the conventional circuit) and by including two dummy unit capacitors connected to ground. The proposed 10-bit ADC is designed and simulated using a 90-nm CMOS technology. Post-layout simulation results show that at 1.0-V supply and 50 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 60.10 dB and consumes 0.32 mW with an input capacitance of 0.48 pF, resulting in a figure of merit (FoM) of 8.44 fJ/conversion-step. The ADC core occupies an active area of 215 × 215 µm²