• DocumentCode
    3012744
  • Title

    Hardware implementation of DBNS recoding for ECC processor

  • Author

    Chabrier, Thomas ; Pamula, Danuta ; Tisserand, Arnaud

  • Author_Institution
    IRISA, Univ. Rennes 1, Lannion, France
  • fYear
    2010
  • fDate
    7-10 Nov. 2010
  • Firstpage
    1129
  • Lastpage
    1133
  • Abstract
    The paper presents arithmetic level protections for ECC processor against some side channel attacks. The proposed protection is based on random recodings of the secret key in the double base number system (DBNS). DBNS is a highly redundant and sparse number system. Here, the high redundancy level of DBNS is used to randomly modify on-the-fly the ki digits during the scalar multiplication [k]P. The proposed solution leads to random numbers and orders of curve level operations (point addition, doubling and tripling) during the computation of [k]P operations. Our random recoding method provides [k]P computation time comparable to the best w-NAF recoding methods. But standard w-NAF recodings are deterministic ones while our solution is a random one.
  • Keywords
    arithmetic codes; public key cryptography; random codes; DBNS recoding; ECC processor; arithmetic level protections; curve level operations; double base number system; random recoding method; scalar multiplication; side channel attacks; sparse number system; standard w-NAF recodings; Computer architecture; Elliptic curve cryptography; Elliptic curves; Field programmable gate arrays; Jacobian matrices;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signals, Systems and Computers (ASILOMAR), 2010 Conference Record of the Forty Fourth Asilomar Conference on
  • Conference_Location
    Pacific Grove, CA
  • ISSN
    1058-6393
  • Print_ISBN
    978-1-4244-9722-5
  • Type

    conf

  • DOI
    10.1109/ACSSC.2010.5757580
  • Filename
    5757580