Temperature aware power optimization for multicore floating-point units

Fused Multiply-Add (FMA) units are quite popular in floating-point execution units in state-of-the-art multicore processors. It has been shown that, for division operations, using digit-recurrence units consumes much less power and energy than using FMA units which are based on Newton-Raphson approximation algorithms. In this work, we show that digit-recurrence division units can also reduce on chip thermal coupling from hot blocks (e.g. FMAs) to cool blocks such as caches. By placing power efficient dividers between FMAs and a cache block, we lower down the average temperature by 5°C in caches and consequently reduce leakage by 12%. The total power consumption in caches is reduced by 8.44%.