Fast, bit-accurate simulation of truncated-matrix multipliers and squarers

Truncated-matrix multipliers and squarers offer significant reductions in area, power, and delay, at the expense of increased computational error. These trade-offs make them an attractive choice for many signal processing systems. However, extensive bit-accurate simulation is often necessary to explore the design space effectively and chose the best parameters when using them in systems. This paper presents an algorithm for fast, bit-accurate simulation of truncated-matrix multipliers and squarers in software. The algorithm is applicable to most correction methods published to date, is simple to implement, and it facilitates research into system-level use of truncated-matrix units.