Title :
Fast, bit-accurate simulation of truncated-matrix multipliers and squarers
Author :
Walters, E. George, III ; Schulte, Michael J.
Author_Institution :
Behrend Coll., Penn State Erie, Erie, PA, USA
Abstract :
Truncated-matrix multipliers and squarers offer significant reductions in area, power, and delay, at the expense of increased computational error. These trade-offs make them an attractive choice for many signal processing systems. However, extensive bit-accurate simulation is often necessary to explore the design space effectively and chose the best parameters when using them in systems. This paper presents an algorithm for fast, bit-accurate simulation of truncated-matrix multipliers and squarers in software. The algorithm is applicable to most correction methods published to date, is simple to implement, and it facilitates research into system-level use of truncated-matrix units.
Keywords :
matrix multiplication; signal processing; bit accurate simulation; correction method; matrix squarer; signal processing system; truncated matrix multiplier; Algorithm design and analysis; Computational modeling; Delay; Discrete cosine transforms; Signal processing; Signal processing algorithms; Space exploration;
Conference_Titel :
Signals, Systems and Computers (ASILOMAR), 2010 Conference Record of the Forty Fourth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
978-1-4244-9722-5
DOI :
10.1109/ACSSC.2010.5757582