Design and Implementation of Integer Transform and Quantization Processor for H.264 Encoder on FPGA

This paper proposes a novel implementation of the core processors, the integer transform and quantization for H.264 video encoder using an FPGA. It is capable of processing the picture frames with the desired compression controlled by the user input. The algorithm and architecture of the components of the video encoder namely, integer transformation, quantization were developed, designed and coded in Verilog. The complete H.264 video encoder was coded in Matlab in order to verify the results of the Verilog implementation. The processor is implemented on a Xilinx Vertex -II Pro XC2VP30 FPGA. The gate count of the implementation is approximately 1,057,000 working at a frequency of 208 MHz. It can process 1024×768 pixel color images in 4:2:0 format at 25 frames per second. The reconstructed picture quality is better than 35 dB.