DocumentCode
3012827
Title
Fault-tolerant designs for 256 Mb DRAM
Author
Kirihata, T. ; Watanabe, Y. ; Wong, H. ; DeBrosse, J. ; Yoshida, M. ; Katoh, D. ; Fujii, S. ; Wordeman, M. ; Poechmueller, P. ; Parke, S. ; Asao, Y.
Author_Institution
Semicond. Res. & Dev. Cemter, IBM Corp., Hopewell Junction, NY, USA
fYear
1995
fDate
8-10 June 1995
Firstpage
107
Lastpage
108
Abstract
Conventional redundancy architecture employs a repair region in each block, and therefore has disadvantages: (1) each block must have at least one (preferably two) redundant row and column, increasing design space; (2) grouped or clustered fails are difficult to repair; (3) a cross fail (WL/BL short-circuit) increases the stand-by current, causing a standby fail. Fault-tolerant designs were developed for a 256 Mb DRAM to overcome these problems by means of a redundancy block, interchangeable Master DQ´s (MDQ´s), and a current limiter.
Keywords
CMOS memory circuits; DRAM chips; fault tolerant computing; integrated circuit reliability; redundancy; 256 Mbit; Mb DRAM; current limiter; fault-tolerant designs; interchangeable Master DQ; redundancy architecture; Circuit simulation; Coupling circuits; Current limiters; Data compression; Fault tolerance; Fuses; Logic; Random access memory; Redundancy; Research and development;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
0-7800-2599-0
Type
conf
DOI
10.1109/VLSIC.1995.520708
Filename
520708
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