A cryogenic single electron transistor readout circuit: Practical issues and measurement considerations

This paper revisits the design of a low power, fast CMOS Single Electron Transistor (SET) readout circuit which can operate at 4.2K and successfully detect 200pA SET signal current with µs detection speed. The design is revised in terms of increased transconductance and charge injection, reduced matching and drain-source resistance and other nonlinearities of the transistor behavior at low temperature. We have reviewed recent developments in cryogenic circuit design and low temperature measurement results found in literature since our previously reported work and used the acquired knowledge to validate our design formulation. We also incorporated possible non-idealities that may arise during the actual low temperature measurement of the fabricated chip. These effects are important since the readout IC requires pA and µV range compliance in order to interface with the SET and also talk to the external lab equipments via long cables.