DocumentCode :
3013147
Title :
Statistical electromigration budgeting for reliable design and verification in a 300-MHz microprocessor
Author :
Kitchin, J.
Author_Institution :
Digital Equipment Corp., Hudson, MA, USA
fYear :
1995
fDate :
8-10 June 1995
Firstpage :
115
Lastpage :
116
Abstract :
Statistical Electromigration Budgeting (SEB) is a novel method for setting and verifying electromigration (EM) design requirements for VLSI interconnect. SEB exploits the statistical nature of EM reliability to selectively supersede fixed current density design rules for some interconnect, allowing increased chip performance while simultaneously quantifying chip-level EM reliability to directly assure design conformance to reliability requirements. The concept and method of SEB are introduced, and some results from its application in the design and verification of the Alpha 21164300 microprocessor are given.
Keywords :
VLSI; electromigration; integrated circuit design; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; microprocessor chips; 300 MHz; Alpha 21164300 microprocessor; EM reliability; VLSI interconnect; chip performance; design conformance; fixed current density design rules; microprocessor design; reliability requirements; statistical electromigration budgeting; Artificial intelligence; Clocks; Current density; Electromigration; Grain size; Integrated circuit interconnections; Life estimation; Microprocessors; Thermal stresses; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
0-7800-2599-0
Type :
conf
DOI :
10.1109/VLSIC.1995.520712
Filename :
520712
Link To Document :
بازگشت