Application-oriented SHA-256 hardware design for low-cost RFID

Cryptographic hash functions can be used to provide strong security and privacy for Radio Frequency Identification (RFID) systems. In this paper, two application-oriented optimized SHA-256 hardware designs for low-cost RFID are presented. These are implemented on UMC 0.13 µm CMOS standard cell technology. One of the proposed designs achieves the smallest area (8,394 gates) while the other achieves the lowest power consumption (2.86 µW) in comparison to previous SHA-256 designs and SHA-3 finalist candidates reported in the literature to date. Furthermore, if the designs are used in low-cost RFID applications in which the input being authenticated is less than 400 bits, the two designs can be further optimized to utilise just 6,125 gates and consume 2.3 µW of power.