DocumentCode :
3013585
Title :
Weight sorting based scheme and architecture for distributed particle filters
Author :
Zheng, Ning ; Pan, Yun ; Yan, Xiaolang ; Huan, Ruohong
Author_Institution :
Institute of VLSI Design, Zhejiang University, Hangzhou, China
fYear :
2012
fDate :
20-23 May 2012
Firstpage :
1472
Lastpage :
1475
Abstract :
This paper presents an efficient weight sorting based scheme and architecture for distributed particle filters (PFs). Instead of redistributing particles among processing elements (PEs) after the resampling step, the proposed scheme sorts the newly generated weights, along with the corresponding propagated particles, in reverse order of the current partial weight sums (PWSs) of PEs so that the final local weight sums in each PE are as close to each other as possible. Resampling is then performed locally in each PE without the redistribution procedure before the next iteration. The corresponding architecture uses two levels of multiplexers to realize the weight/state sorting operation, and features regular structure, low execution time, high memory efficiency and well scalability.
Keywords :
Memory management; Multiplexing; Particle filters; RNA; Scalability; Sorting;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location :
Seoul, Korea (South)
ISSN :
0271-4302
Print_ISBN :
978-1-4673-0218-0
Type :
conf
DOI :
10.1109/ISCAS.2012.6271525
Filename :
6271525
Link To Document :
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