High speed 1-D FIR digital filtering architectures using polynomial convolution

Two sets of 1-D FIR digital filtering architectures are proposed to reduce computational complexity and to increase throughput rate. Each architecture is regular in structure with a high degree of parallelism and pipelining. Consequently, they are suitable for VLSI or multiprocessor implementation. In the paper, infinite linear convolution is first converted into finite length linear or cyclic convolution in polynomial ring. Certain algorithms that are used to reduce computational complexity in finite length linear or cyclic convolution can then be applied here to reduce computational complexity of polynomial convolution and give the resulting filter structure.