Low complexity FFT/IFFT processor for high-speed OFDM system using efficient multiplier scheduling

In this paper, we propose an enhanced eight-parallel 128/256-point mixed-radix multi-path delay commutator (MRMDC) FFT/IFFT processor for high-speed orthogonal frequency-division multiplexing (OFDM) systems to reduce the number of complex multipliers. The proposed processor can achieve a high throughput rate by using an eight-parallel data-path scheme and an efficient scheduling scheme of complex multiplications. The efficient scheduling scheme can reduce the total number of complex multipliers by about 41%. The proposed eight-parallel FFT/IFFT processor has been designed and implemented with the 90 nm CMOS technology. It can reduce the gate count up to 16% and provide a throughput rate of up to 27.5 Gsamples/s.