DocumentCode
3014142
Title
A 1-V high-speed MTCMOS circuit scheme for power-down applications
Author
Shigematsu, S. ; Mutoh, S. ; Matsuya, Y. ; Yamada, J.
Author_Institution
NTT LSI Labs., Atsugi, Japan
fYear
1995
fDate
8-10 June 1995
Firstpage
125
Lastpage
126
Abstract
A new MTCMOS concept is proposed for power-down applications. This concept realises a new circuit scheme to hold data during the power-down period in which the power is not supplied. Low-power, high-speed performance are achieved by separating the holding circuit from the critical path. A scan register has been developed based on this concept. Using this scheme for an LSI chip, 20-MHz operation at 1.0 V and only a few nA standby current was achieved with 0.5-/spl mu/m CMOS technology.
Keywords
CMOS integrated circuits; large scale integration; power integrated circuits; 0.5 micron; 1 V; 20 MHz; LSI chip; critical path; high-speed MTCMOS circuit; holding circuit; low-power electronics; multi-threshold CMOS technology; power-down; scan register; standby current; Automatic testing; CMOS technology; Clocks; Large scale integration; Latches; Leakage current; Logic circuits; MOSFETs; Power supplies; Sleep;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
0-7800-2599-0
Type
conf
DOI
10.1109/VLSIC.1995.520717
Filename
520717
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