A hardware pyramid vector quantizer

A single-chip, dedicated processor for implementation of pyramid vector quantization is presented. The computational requirements of the vector quantizer encoding algorithm are described, and a processor architecture and instruction set selected for efficient implementation of the vector quantization. The processor performance is characterized by analysis and simulation, with a general conclusion that for a state-of-the-art VLSI implementation, 64 dimensional vectors can be vector quantized at a sample rate of 16 kHz.