A Novel Algorithm for Nesting of 3-Dimensional Parts

The nesting of 3-dimensional parts problem is important for practical applications. In the field of VLSI design, the nesting of 3-dimensional parts problem arises from both the packing of the 3-D integrated circuits and the task schedule of FPGA design. In this paper, we propose a novel floor plan representation, named 3-Dimensional Corner Layout List to encode the topology of the 3-D nesting. Based on triple string, we can represent general nesting including slicing and nonslicing. Our algorithm is very effective that the transformation from 3D layout list to the real nesting need only linear time computation effort. Based on simulated annealing algorithm, we can optimize the 3D nesting effectively. Experimental results show that our algorithm is effective and efficient.