Energy metrics for power efficient crosslink and mesh topologies

Clock distribution networks are an essential element of a synchronous digital circuit, a significant power consumer and highly sensitive to process, voltage, and temperature variations. Mesh- and crosslink-based topologies reliably compensate for skew variations in these networks, albeit with a significant increase in dissipated power as compared to variation-sensitive low power clock trees. Existing crosslink-based methods, however, only address skew from an algorithmic perspective at the network topology level. Guidelines for inserting crosslinks within a buffered low power clock tree are provided in this paper. Physical constraints, such as the size of the crosslink and exact location between the driving and load buffers, are analytically described. Metrics to determine the most energy efficient non-tree topology are provided based on closed-form expressions, and verified with simulation.