Vector quantizer architectures for speech and image coding

We present a number of architectures for vector quantization (VQ) of speech and images using VLSI and VHSIC technologies. A Dual Distortion Processor Module (DPM) has been designed to compute the error vectors at a rate of 10 million vector operations per second in a systolic configuration. An array processor controller (APC) administers the system and determines the nearest neighbor matching codeword in either a full-search or a tree-search manner. A real-time system was built and tested in 0.5 bit per pixel (bpp) image coding application. We also present an architecture using VHSIC technology based on fuzzy associative memory (FAM) chips. In this case, the system has been configured in a VME bus environment and the overall number crunching task is handled by VHSIC chips.