Designing a high complexity microprocessor using the Alliance CAD system

Author

Greiner, Alain ; Lucas, Luis ; Wajsbürt, Franck

Author_Institution

Lab. MASI, Univ. Pierre et Marie Curie, Paris, France

fYear

1994

fDate

19-23 Sep 1994

Firstpage

223

Lastpage

226

Abstract

This paper presents the design methodology for a Superscalar 128-bit Very Long Instruction Word (VLIW) processor. A full set of portable cell libraries, macro-block generators associated with complex and advanced tools, such as logic synthesis, functional abstractor, formal proof tool and data-path compiler have been used in order to achieve a fast design cycle, and still maintain a high level of integration and performance. The final circuit contains about 875,000 transistors with a die size of 14.6 * 14.6 mm² in a 0.8 μm process

Keywords

VLSI; circuit CAD; integrated circuit design; logic CAD; microprocessor chips; parallel architectures; 0.8 micron; 128 bit; Alliance CAD system; data-path compiler; design cycle; design methodology; die size; formal proof tool; functional abstractor; high complexity microprocessor; logic synthesis; macro-block generators; portable cell libraries; superscalar VLIW processor; very long instruction word; Application specific integrated circuits; Circuit simulation; Design automation; Design methodology; Hardware design languages; Microprocessors; Registers; Silicon; Switches; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-2020-4

Type

conf

DOI

10.1109/ASIC.1994.404571

Filename

404571