Design of a scalable parallel switch-level simulator for VLSI

The problem of mapping a computation-intensive task of irregular structure onto a parallel framework is examined. The application considered is the switch-level logic simulation of digital circuits, a technique that is in wide use for the verification of VLSI designs. The authors focus on medium-grain multiprocessors and only consider model parallel computation, where the model of the design to be simulated is partitioned among processors. They address the issues of portability and scalability and look at specific features of the application that can be exploited. Different ways of mapping the simulation problem onto a parallel framework are presented. A prototype implementation of the algorithms is described