DocumentCode :
3014913
Title :
A 1-V CMOS receiver front-end for high-speed SI-POF links
Author :
Gimeno, C. ; Aldea, C. ; Celma, S. ; Aznar, F. ; Azcona, C.
Author_Institution :
Group of Electronic Design - Aragón Institute of Engineering Research (GDE-I3A), Universidad de Zaragoza, E-50009, Spain
fYear :
2012
fDate :
20-23 May 2012
Firstpage :
1732
Lastpage :
1735
Abstract :
This paper presents a new analog front-end for short-reach high-speed optical communications. It compensates the limited bandwidth of SI-POF transmission systems. In particular, the front end has been designed using a cost-effective 0.18-µm CMOS technology and fed with only 1V. The proposed architecture, formed by a transimpedance amplifier and a continuous-time equalizer, targets 1.25 Gb/s transmission for a simple NRZ modulation in an optical link composed of 50 m of SI-POF and a large area Si PIN photodetector.
Keywords :
Bandwidth; CMOS integrated circuits; CMOS technology; Equalizers; Gain; Optical fiber communication; Optical fibers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location :
Seoul, Korea (South)
ISSN :
0271-4302
Print_ISBN :
978-1-4673-0218-0
Type :
conf
DOI :
10.1109/ISCAS.2012.6271597
Filename :
6271597
Link To Document :
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