DocumentCode
3015162
Title
Design of TETRA 2 turbo decoder with minimum memory hardware interleaver
Author
Kim, Ji-Hoon
Author_Institution
Dept. of Electronics Engineering, Chungnam National University, Daejeon 305-764, Republic of Korea
fYear
2012
fDate
20-23 May 2012
Firstpage
1779
Lastpage
1782
Abstract
Terrestrial Trunked Radio (TETRA) is a digital trunked mobile radio standard developed by the European Telecommunications Standards Institute (ETSI). Especially, TETRA 2 supports different channel bandwidths and modulation techniques, and turbo code has been adopted as a channel code with powerful error correcting capability. In this paper, to lower the implementation cost of Takeshita-Costello interleaver adopted in TETRA 2, we present the simple interleaved address generation scheme which requires minimum memory size compared to the conventional memory-based interleaver. Also, overall TETRA 2 turbo decoder architecture including the proposed interleaver is described with its implementation results
Keywords
Decoding; Hardware; Memory management; Random access memory; Telecommunication standards; Turbo codes;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location
Seoul, Korea (South)
ISSN
0271-4302
Print_ISBN
978-1-4673-0218-0
Type
conf
DOI
10.1109/ISCAS.2012.6271610
Filename
6271610
Link To Document