Title :
Charge trapping in interpoly ONO film
Author :
Lim, K.S. ; Ling, C.H.
Author_Institution :
Dept. of Electr. Eng., Nat. Univ. of Singapore, Singapore
Abstract :
The stacked capacitor structure used in DRAM cells usually takes the form of an interpoly capacitor where the dielectric layer is sandwiched between two polycrystalline silicon plates. The charge trapping characteristics of the oxide-nitride-oxide (ONO) film in an interpoly capacitor structure has been investigated. The hole trapping characteristics are observed under constant current stress. The trapped charge centroid is found to be localised at the top oxide/nitride interface under both stress polarities. The larger hole trapping observed under negative stress correlates to a shorter electrical lifetime
Keywords :
DRAM chips; capacitors; dielectric thin films; electric current; hole traps; integrated circuit testing; interface states; DRAM cells; Si-SiO2-Si3N4-SiO2-Si; charge trapping; charge trapping characteristics; constant current stress; dielectric layer; electrical lifetime; hole trapping; hole trapping characteristics; interpoly ONO film; interpoly capacitor; interpoly capacitor structure; oxide-nitride-oxide film; polycrystalline silicon plates; stacked capacitor structure; stress polarity; top oxide/nitride interface; trapped charge centroid; Capacitors; Dielectrics; Random access memory; Semiconductor films; Silicon; Substrates; Temperature measurement; Testing; Thermal stresses; Voltage;
Conference_Titel :
Semiconductor Electronics, 1998. Proceedings. ICSE '98. 1998 IEEE International Conference on
Conference_Location :
Bangi
Print_ISBN :
0-7803-4971-7
DOI :
10.1109/SMELEC.1998.781147
